1. Field of the Invention
The present invention relates to an analog-to-digital (AD) converter (ADC). Moreover, the present invention relates to a solid-state imaging apparatus having an AD converter and used in a digital camera, a digital video camera, an endoscope, etc.
2. Description of Related Art
As an example of an AD converter for use in a conventional solid-state imaging apparatus, an AD converter 1000 illustrated in FIG. 13 is known (for example, see the publication of Japanese Unexamined Patent Application, First Publication No. 2009-38781 and the publication of Japanese Unexamined Patent Application, First Publication No. 2009-38726). As illustrated in FIG. 13, the AD converter 1000 has a clock generation section 101, a reference signal generation section 102, a comparator 103, a latch section 104, a counter 105, and a timing control section 106.
The clock generation section 101, for example, includes a delay control circuit (delay lock loop (DLL)). The clock generation section 101 generates a plurality of clock signals (multi-phase clocks) CK0 to CK3 having different phases from each other. The reference signal generation section 102 generates a reference signal RAMP whose level changes in an inclined shape with the passage of time in synchronization with an output of the clock generation section 101.
The comparator 103 receives a pixel signal Vpix serving as a target of time detection and the reference signal RAMP and outputs a comparison signal Vco which is a pulse signal having a magnitude (pulse width) of a time axis direction corresponding to a magnitude of the pixel signal Vpix. The comparator 103 is connected to power supply wiring 109 through which a power supply voltage Vdd is applied.
The latch section 104, for example, has a plurality of latch units 107 constituted of D-latches. The plurality of latch units 107 are connected to the comparator 103 through the latch control signal line 108. The plurality of latch units 107 receive the comparison signal Vco from the comparator 103 and latch the clock signals CK0 to CK3 at the timing at which the comparison signal Vco is inverted.
The counter 105 performs a count operation based on a signal Latch0 output from one latch unit 107 of the latch section 104. The signal Latch0 is a signal output from the latch unit 107 to which the clock signal CK0 is input from the clock generation section 101 and is a signal equivalent to the clock signal CK0.
Next, an operation of the AD converter 1000 will be described using FIG. 14. FIG. 14 illustrates an operation example of the AD converter 1000. In FIG. 14, the reference signal RAMP, the pixel signal Vpix, the comparison signal Vco, the clock signals CK0 to CK3, signals Latch0 to Latch3, and a count value are illustrated. The signals Latch0 to Latch3 indicate states of signals inside four latch units 107 to which the clock signals CK0 to CK3 are input. The horizontal direction of FIG. 14 represents time. In addition, the vertical direction of FIG. 14 represents a voltage for each signal excluding the count value.
First, at a timing T1 related to an operation start, the clock generation section 101 starts an operation. Thereby, the reference signal generation section 102 starts an output of the reference signal RAMP. The clock signals CK0 to CK3 from the clock generation section 101 are input to the latch units 107. One latch unit 107 outputs the clock signal CK0 as the signal Latch0 to the counter 105. The counter 105 performs the count operation based on the signal Latch0. In the example illustrated in FIG. 14, the counter 105 performs the count operation at a rising edge of the signal Latch0.
At the timing T1, the level of the reference signal RAMP is higher than the level of the pixel signal Vpix. After the timing T1, the level of the reference signal RAMP decreases with the passage of time. At the timing T2 at which the level of the reference signal RAMP is lower than the level of the pixel signal Vpix, the level of the comparison signal Vco from the comparator 103 is inverted from a Low level to a High level. Thereby, the plurality of latch units 107 hold states of the clock signals CK0 to CK3. The plurality of latch units 107 hold the states of the clock signals CK0 to CK3 and therefore the counter 105 holds the count value.
As described above, the AD converter 1000 obtains digital data corresponding to the magnitude of the pixel signal Vpix. The digital data includes the count value held by the counter 105 and the states of the clock signals CK0 to CK3 held by the plurality of latch units 107.